Model Verification and Validation
In the following, verification is defined as an activity to confirm the fulfillment of requirements. Validation is defined as an activity to confirm that the specific intended use of the model is accomplished.
The verification and validation (V&V) process should always follow the same top-down process as the model design refer to Functional System Design Methodology Roadmap), i.e. the model should be verified and validated before proceeding to the next level of decomposition.
The following summarizes the steps to follow in the V&V process.
Verification and Validation on Chart Level: Verification and Validation on Module/Sub-System and System Level:
• Identify the normal operations of the system from the requirements.
• Simulate the normal operations of the chart, record simulation script files, record input and output patterns, and use trace files to examine state coverage in the waveform viewer.
• Modify the recorded script files and create additional test scripts if necessary.
• Playback the newly created script files, record input and output patterns, and use trace files to examine state coverage in the waveform viewer.
• Simulate the boundary cases and failure conditions, record simulation script files, record input and output patterns, and use trace files to examine state coverage in the waveform viewer.
• Modify the recorded script files and create additional test scripts if necessary.
• Playback the newly created script files, record input and output patterns, and use trace files to examine state coverage in the waveform viewer.
• Generate Prototype code from the model and ensure the generated code behaves the same as the model by comparing the output stimulus pattern with the output pattern from simulation.Note: On the system level, the V&V efforts should focus on the communication among the parts of the system, and not attempt to duplicate all of the chart level testing.